The present disclosure relates to semiconductor devices used in semiconductor integrated circuits, and more particularly, to techniques of improving characteristics of paired transistors included in a differential circuit etc.
A semiconductor integrated circuit device includes a large number of paired transistors forming a differential amplifier circuit, a current mirror circuit, etc. The difference in characteristics between the paired transistors has an influence on the performance, yield, etc. of the circuit.
In particular, when an isolation technique, such as shallow trench isolation (STI) etc., is used to fabricate a transistor, the channel mobility or the threshold voltage of the transistor varies depending on STI-induced mechanical stress applied on the active region of the transistor. Therefore, it is known that when paired transistors have active regions having different shapes, the difference in characteristics between the paired transistors is significant (see, for example, “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress,” G. Scott, et. al., IEDM digest, pp. 91, 1999).
When gate electrodes are formed by a lithography process or an etching process, a dimension of a gate electrode may be altered by the layout pattern of its surrounding gate electrodes, leading to a difference in characteristics. In recent years, there has been a known technique of covering upper portions of the gate electrode and the active region with a highly strained film to improve the drive performance of a transistor. In this technique, however, the influence of stress may vary depending on the gate electrodes of paired transistors or the layout pattern of their surrounding gate electrodes, leading to a difference in characteristics (see “High Performance CMOSFET Technology for 45 nm Generation and Scalability of Stress-Induced Mobility Enhancement Technique,” A. Oishi, et. al., IEDM digest, pp. 239, 2005).
In conventional semiconductor devices, in order to reduce the difference in characteristics between paired transistors, the paired transistors may be located at perfectly symmetric positions to reduce a difference in characteristics which is caused by a difference in layout pattern, for example.
For example, as shown in FIG. 21, paired transistors 100a and 100b are provided with dummy elements 102a and 102b having the same shape as that of a transistor 101 adjacent to the transistors 100a and 100b in the channel length direction being provided on opposite sides of the transistors 100a and 100b. Similarly, dummy elements 104a and 104b having the same shape as that of a transistor 103 adjacent to the transistor 100a are provided at the same distance from the transistors 100a and 100b in the channel width direction, respectively. By thus providing the same surrounding layout to the paired transistors, the imbalance in characteristics between the paired transistors is reduced or prevented (see Japanese Patent Publication No. H11-234109).